Research Topic

Towards noise-driven computing architectures for coarse-grained devices and materials

Research Aim

The object of this research group is the development of a new information processing architectural design that possesses ‘coarse-grained devices’ as calculation elements. ‘Coarse-grained device’ here refers to a device with characteristic variations and fluctuations (ambiguity).

Role and Need in the Group

The role of this group is to combine the characteristics (fluctuation and non-linearity) of the molecular devices that the A01-03 groups have developed and elucidate the elements that can be included in coarse-grain elements, system architectonics, and their combinations. Tight cooperation within these research areas is indispensable for the creation of an ‘exit-oriented hierarchical information processing systems design’ that could not have been accomplished in a single area.

Research Content

We will establish a circuit and systems design for coarse-grained elements. In order to expand the use of coarse-grained elements to new nano-integrated information processing system applications, we will engage in research in the following areas: implementation of logical operation circuits and early brain-like information processing circuits using coarse-grained elements; elucidation of the physics of stochastic resonance gates that are the foundation of circuit applications using coarse-grained elements; and the probability of the design methods of brain-like asynchronous logic circuits that combine stochastic resonance gates.a04-3.jpg



Research representative: Tetsuya Asai Professor / Hokkaido University Graduate School of Information Science and Technology
Member of the research project: Takahide Oya Associate Professor / Yokohama National University Graduate School of Engineering

Papers List


[9] A molecular neuromorphic network device consisting of single-walled carbon nanotubes complexed with polyoxometalate [重要文献]

Hirofumi Tanaka; Megumi Akai-Kasaya; Amin TermehYousefi; Liu Hong; Lingxiang Fu; Hakaru Tamukoh; Daisuke Tanaka; Tetsuya Asai; Takuji Ogawa
Nature Communications, 9, 2693, 2018/7/12
DOI: 10.1038/s41467-018-04886-2


[8] Design and evaluation of single-electron associative memory circuit [重要文献]

M. Takano; T. Asai; T. Oya
International Journal of Parallel, Emergent and Distributed Systems, 259 - 270, 2016
DOI: 10.1080/17445760.2016.1165219


[7] Memristor-CMOS-hybrid synaptic devices exhibiting spike-timing-dependent plasticity

Asai T.
VLSI: Circuits for Emerging Applications (Eds. Wojcicki T. and Iniewski I. ), , 2014

[6] Explorations in Morphic Architectures

Asai T.; Peper F.
Emerging Nanoelectronic Devices( Ed.Chen A.), in press, , 2014

[5] Reaction-diffusion media with excitable Oregonators coupled by memristors

Asai T.
Memristor Networks ( Eds. Adamatzky A. and Chua L. ), in press, , 2014

[4] FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to motion classification with neural networks

Mori M. ; Itou T.; Ikebe M.; Asai T.; Kuroda T.; Motomura M.
Journal of Signal Processing, 18, in press, , 2014


[3] FPGA implementation of single-image super resolution based on frame-bufferless box filtering

Sanada Y.; Ohira T.; Chikuda S.; Igarashi M.; Ikebe M.; Asai T.; Motomura M
Journal of Signal Processing, 17, 4, 111 - 114, 2013/7/39
DOI: 10.2299/jsp.17.111

[2] Chaotic resonance in forced Chua's oscillators [重要文献]

Ishimura K.; Asai T.; Motomura M.
Journal of Signal Processing, 17, 6, 231 - 238, 2013/11/25
DOI: 10.2299/jsp.17.231

[1] C-based design of window join for dynamically reconfigurable hardware

Fukuda E.S.; Kawashima H.; Inoue H.; Asai T.; Motomura M
Journal of Computer Science and Engineering, 20, 2, 1 - 9, 2013/11