Tetsuya Tetsuya | Orchestration of Single Molecules for Novel Function

Asai Tetsuya
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Web：http://lalsie.ist.hokudai.ac.jp/~asai/

Group	Group A04 Design and measurement of cooperative functions
Research Topic	Towards noise-driven computing architectures for coarse-grained devices and materials
Position in Group	Research representative
Title	Professor
Affiliation	Hokkaido University Graduate School of Information Science and Technology LINAS
Address	060-0814 Kita 14, Nishi 9, Kita-ku, Sapporo, 060-0814, Japan
TEL	（Log in user only）
FAX	（Log in user only）
Research Areas	Integrated Circuit Engineering, Nonlinear Science
Keywords	emerging research architecture, noise-driven computing, neuromorphic information processing

Papers List

2018

[9] A molecular neuromorphic network device consisting of single-walled carbon nanotubes complexed with polyoxometalate [重要文献]

Hirofumi Tanaka; Megumi Akai-Kasaya; Amin TermehYousefi; Liu Hong; Lingxiang Fu; Hakaru Tamukoh; Daisuke Tanaka; Tetsuya Asai; Takuji Ogawa
Nature Communications, 9, 2693, 2018/7/12
DOI: 10.1038/s41467-018-04886-2

2016

[8] Design and evaluation of single-electron associative memory circuit [重要文献]

M. Takano; T. Asai; T. Oya
International Journal of Parallel, Emergent and Distributed Systems, 259 - 270, 2016
DOI: 10.1080/17445760.2016.1165219

2014

[7] Memristor-CMOS-hybrid synaptic devices exhibiting spike-timing-dependent plasticity

Asai T.
VLSI: Circuits for Emerging Applications (Eds. Wojcicki T. and Iniewski I. ), , 2014

[6] Explorations in Morphic Architectures

Asai T.; Peper F.
Emerging Nanoelectronic Devices( Ed.Chen A.), in press, , 2014

[5] Reaction-diffusion media with excitable Oregonators coupled by memristors

Asai T.
Memristor Networks ( Eds. Adamatzky A. and Chua L. ), in press, , 2014

[4] FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to motion classification with neural networks

Mori M. ; Itou T.; Ikebe M.; Asai T.; Kuroda T.; Motomura M.
Journal of Signal Processing, 18, in press, , 2014

2013

[3] FPGA implementation of single-image super resolution based on frame-bufferless box filtering

Sanada Y.; Ohira T.; Chikuda S.; Igarashi M.; Ikebe M.; Asai T.; Motomura M
Journal of Signal Processing, 17, 4, 111 - 114, 2013/7/39
DOI: 10.2299/jsp.17.111

[2] Chaotic resonance in forced Chua's oscillators [重要文献]

Ishimura K.; Asai T.; Motomura M.
Journal of Signal Processing, 17, 6, 231 - 238, 2013/11/25
DOI: 10.2299/jsp.17.231

[1] C-based design of window join for dynamically reconfigurable hardware

Fukuda E.S.; Kawashima H.; Inoue H.; Asai T.; Motomura M
Journal of Computer Science and Engineering, 20, 2, 1 - 9, 2013/11